1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of the Related Art
U.S. Pat. No. 6,063,688 discloses a method of manufacturing a plurality of transistors of dimensions below the limits of lithographic techniques by forming gate electrodes and the like using processing hard masks formed on the sidewalls of dummy pattern structures.
Japanese Unexamined Patent Publication No. 8-55920 also discloses a method of manufacturing a plurality of transistors of dimensions below the limits of lithographic techniques, which involves forming a conductive film on a semiconductor substrate, forming a first mask layer on the conductive film, patterning the first mask layer to form strip-like patterns, forming a second mask layer on the conductive film and the strip-like patterns, carrying out anisotropic etching on the second mask layer so that it is left only on the sidewalls of the strip-like patterns, removing the strip-like patterns, and selectively etching the conductive film using the second mask layer as a mask. This publication also discloses a method of manufacturing a semiconductor device having a plurality of nonvolatile memory cells by applying the selective etching process using the second mask layer as a mask to a pattering process for forming control and floating gate electrodes.
However, with the techniques disclosed in the above publications, there is a problem that variations in performance occur among transistors formed in the semiconductor substrate.